1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to the fabrication of metal gate electrodes and semiconductor resistors for CMOS devices.
2. Description of the Related Art
As the size and scaling of semiconductor device technology is reduced, aspects of device design and fabrication that previously gave rise to only second-order effects in long-channel devices can no longer be ignored. For example, the reduced scaling of channel length and gate oxide thickness in a conventional MOS transistor exacerbates problems of polysilicon gate depletion, high gate resistance, high gate tunneling leakage current and dopant (i.e., boron) penetration into the channel region of the device. As a result, CMOS technology is increasingly replacing silicon dioxide gate dielectrics and polysilicon gate conductors with high dielectric constant (high-k) dielectrics in combination with metal gate electrodes formed from a gate stack of polysilicon and one or more metal layers. With such technologies, the metal gate layers not only obviate gate-depletion and boron-penetration effects, but also provide a significantly lower sheet resistance. However, due to the relatively high conductivity of the metal gate layers, the metal gate layers must typically be removed from the area where polysilicon resistors are formed since the higher conductivity of the metal gate layer detrimentally lowers the resistance of the polysilicon resistors, thereby requiring additional processing steps to selectively remove the metal layer in the resistor area by patterning a hard mask layer to expose the metal layer and then etching the exposed metal layer so that the subsequently deposited polysilicon layer is not formed over the metal gate layer in the resist area. In addition to adding complexity and cost to the fabrication process, the resulting structure has different stack heights in the transistor and resistor areas which can adversely impact subsequent processing. To provide an illustrative example, reference is made to FIG. 1 which shows a cross section of a semiconductor structure 1 in which a transistor gate electrode 17 and semiconductor resistor 18 are formed on a silicon substrate 10. As illustrated, isolation regions 12, 13 are formed in the surface of substrate 10, such as by forming field oxide or shallow trench isolation regions. The isolation regions 12, 13 define and electrically isolate active surface regions in the surface of substrate 10 where the transistor(s) will ultimately be formed. In addition, the isolation region 13 defines the surface on which the semiconductor resistor 18 is formed. After the isolation regions 12, 13 are formed, a gate dielectric layer 14 is formed over the semiconductor structure, followed by the deposition of a metal layer 15 over the gate dielectric layer. However, prior to forming the semiconductor layer 16, the metal gate layer must be removed from the resistor area, such as by applying and patterning a hard mask to expose the metal layer 16 over the isolation region 13, and then etching the exposed metal layer 16 from the resistor area. Having removed the metal layer from the resistor area, the subsequently deposited semiconductor layer 16 is formed on the metal gate layer 15 in the transistor area, but is formed on the gate dielectric layer 14 in the resistor area. With this stack in place, the subsequent pattern and etch processes result in a height differential between the transistor gate electrode 17 and semiconductor resistor 18.
Accordingly, a need exists for an improved poly/metal gate electrode and manufacture method for manufacturing MOSFET devices in which integrated semiconductor resistors are formed. In addition, there is a need for improved semiconductor device structure and manufacturing process to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.